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| LH7A404 Advance Data Sheet FEATURES * ARM922TTM Core: - 32-bit ARM9TDMITM RISC Core (200 MHz) - 16KB Cache: 8KB Instruction Cache and 8KB Data Cache - MMU (Windows CETM Enabled) * 80KB On-Chip Memory * Vectored Interrupt Controller * External Bus Interface - 100 MHz - Asynchronous SRAM/ROM/Flash - Synchronous DRAM/Flash - PCMCIA - Compact Flash * Clock and Power Management - 32.768 kHz and 14.7456 MHz Oscillators - Programmable PLL * Low Power Modes - Run (200 mA), Halt, Standby (35 A) * Programmable LCD Controller - Up to 1,024 x 768 Resolution - Supports STN, Color STN, HR-TFT, TFT - Up to 64 k-Colors and 15 Gray Shades * 10 Channel, 10-bit A/D Converter - Touch Screen Controller - Brownout Detector * DMA (12 Channels) - External DMA Channels - AAC (AC97) - MMC - USB * USB Host and Device Interface (USB1.1) 32-Bit System-on-Chip * Synchronous Serial Port (SSP) - Motorola SPITM - Texas Instruments SSI - National MICROWIRETM * PS/2 Keyboard/Mouse Interface (KMI) * Three Programmable Timers * Three UARTs - Classic IrDA (115 kbit/s) * Smart Card Interface (ISO7816) * Four Pulse Width Modulators (PWMs) * MultiMediaCard Interface with Secure Digital (MMC 2.11/SD 1.0) * AAC (AC97) Codec Interface * Smart Battery Monitor Interface * Real Time Clock (RTC) * Up to 64 General Purpose I/O Channels * Programmable Interrupt Controller * Watchdog Timer * JTAG Debug Interface and Boundary Scan * Operating Voltage - 1.8 V Core - 3.3 V Input/Output (1.8 V I/O Optional*) * Temperature - 0C to +70C Commercial - -40C to +85C Industrial (With Clock Frequency Reduction*) * 324-Ball PBGA Package DESCRIPTION The advent of 3G technology opens the door for a wide range of Multimedia applications in mobile information appliances. These appliances require high processing performance and low power consumption. The LH7A404 is designed from the ground up to provide high processing performance, low power consumption, and a high level of integration. The LH7A404 contains a high performance 32-bit ARM922T Core. Power consumption is reduced by the high level of integration, 80KB on-chip SRAM, fully static design, power management unit, low voltage operation (1.8 V Core, 1.8 V or 3.3 V I/O) and on-chip PLL. Motorola SPI is a trademark of Motorola, Inc. National Semiconductor MICROWIRE is a trademark of National Semiconductor Corporation. ARM922T and ARM 9TDMI are trademarks of Advanced RISC Machines (ARM) Ltd. Windows CE is a trademark of Microsoft Corporation. NOTE: *Under development. Results pending further characterization. Advance Data Sheet 1 LH7A404 32-Bit System-on-Chip 14.7456 MHz 32.768 kHz OSCILLATOR, PLL1 and PLL2, POWER MANAGEMENT, and RESET CONTROL REAL TIME CLOCK WATCHDOG TIMER TIMER (3) ARM 922T VECTORED INTERRUPT CONTROLLER ASYNCHRONOUS MEMORY CONTROLLER EXTERNAL BUS INTERFACE PCMCIA/CF CONTROLLER ADVANCED PERIPHERAL BUS BRIDGE GENERAL PURPOSE I/O (64) SYNCHRONOUS SERIAL PORT BATTERY MONITOR INTERFACE UART (3) IrDA INTERFACE USB DEVICE INTERFACE MULTIMEDIA CARD/ SECURE DIGITAL INTERFACE AC97 CODEC INTERFACE SMART CARD INTERFACE (ISO7816) SYNCHRONOUS MEMORY CONTROLLER LCD AHB BUS 80KB SRAM COLOR LCD CONTROLLER DMA CONTROLLER HR-TFT LCD TIMING CONTROLLER USB HOST INTERFACE COLOR LCD CONTROLLER ADVANCED HIGH-PERFORMANCE BUS (AHB) ADVANCED PERPHERAL BUS (APB) PWM (4) A/D TOUCH SCREEN CONTROLLER PS/2 INTERFACE LH7A404-1 Figure 1. LH7A404 Block Diagram 2 Advance Data Sheet 32-Bit System-on-Chip LH7A404 Table 1. Functional Pin List BGA J9 K9 M9 N9 P9 P11 P12 P13 P14 N14 M14 L14 K14 J14 J13 J11 J10 E4 H4 L4 R4 W8 W11 W15 W19 T19 P19 M19 K19 G19 D18 D14 D10 D7 K3 Y5 Y12 V20 N20 H20 D20 C12 C8 F3 VDDC Core Power VSS I/O Ring Ground VDD I/O Ring Power SIGNAL DESCRIPTION OUTPUT DRIVE Advance Data Sheet 3 LH7A404 32-Bit System-on-Chip Table 1. Functional Pin List (Cont'd) BGA G2 M2 AA6 AA15 P21 K21 F21 B17 B10 B5 AA17 VDDA1 AB17 VSSA1 AA18 VDDA2 AB18 VSSA2 AB16 VDDA3 AB13 VSSA3 D3 E3 D4 E1 C2 Y16 Y20 L3 N13 Y21 Y22 nPOR nURESET WAKEUP nPWRFL nEXTPWR XTALOUT XTAL32OUT PGMCLK nCS1 nCS2 nCS6 Analog Power for PLL1 Analog Ground for PLL1 Analog Power for PLL2 Analog Ground for PLL2 Analog Power for A/D, Touch Screen Controller Analog Ground for A/D, Touch Screen Controller Power on Reset User Reset Wake Up Power Fail Signal External Power 14.7456 MHz Crystal Oscillator pins. To drive the device from an external clock source, XTALIN can be used while XTALOUT is left unconnected. 32.768 kHz Real Time Clock, Crystal Oscillator pins. To drive the device from an external clock source, XTAL32IN can be used while XTAL32OUT is left unconnected. Programmable Clock (14.7456 MHz MAX.) Asynchronous Memory Chip Select 0 (ROM/Flash) Asynchronous Memory Chip Select 1 Asynchronous Memory Chip Select 2 Asynchronous Memory Chip Select 3 and MMC Select Asynchronous Memory Chip Select 6 Asynchronous Memory Chip Select 7 8 mA 16 mA 16 mA 16 mA 16 mA 16 mA 16 mA 2 mA VSSC Core Ground SIGNAL DESCRIPTION OUTPUT DRIVE AA16 XTALIN AA21 XTAL32IN AB22 nCS0 W20 nCS3/nMMCSEL W21 nCS7 4 Advance Data Sheet 32-Bit System-on-Chip LH7A404 Table 1. Functional Pin List (Cont'd) BGA W22 D0 V21 U22 U20 T22 T20 R21 R19 P20 N21 M22 M20 L21 L19 K20 J21 J19 H21 G22 G20 F20 E22 E20 D22 C22 B22 B21 D19 B20 A20 B19 B18 A1 V22 V19 U21 U19 T21 R22 R20 P22 N22 N19 M21 L22 L20 K22 J22 J20 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 TDI A0 A1 A2/SA0 A3/SA1 A4/SA2 A5/SA3 A6/SA4 A7/SA5 A8/SA6 A9/SA7 A10/SA8 A11/SA9 A12/SA10 A13/SA11 A14/SA12 A15/SA13 Address Bus and Synchronous Address Bus 16 mA JTAG Data In. This signal should be pulled-up to VDD Address Bus 16 mA Data Bus 16 mA SIGNAL DESCRIPTION OUTPUT DRIVE Advance Data Sheet 5 LH7A404 32-Bit System-on-Chip Table 1. Functional Pin List (Cont'd) BGA H22 H19 G21 F22 F19 E21 E19 D21 C21 A18 A17 C17 C14 A13 M13 A16 B16 C16 D16 A22 C20 A21 C19 A19 M3 M1 N4 N3 N2 N1 P4 P3 P2 L10 L11 M10 M11 N10 P1 R1 R2 R3 T1 T2 T3 T4 U1 U2 SIGNAL A16/SBANK0 A17/SBANK1 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 nOE nWE0 nWAIT SCKEN3 SCLK SCKE1 SCKE0 nSCS0 nSCS1 nSCS2 nSCS3 nSWE PA0/LCDVD16 PA1/LCDVD17 PA2 PA3 PA4 PA5 PA6 PA7 PB0/UARTRXD1 PB1/UARTTXD3 PB2/UARTRXD3 PB3/UARTCTS3 PB4/UARTDCD3 PB5/UARTDSR3 PB6/BMISWIB/BMISMBIO PB7/BMISMBCLK PC0/TXD1 PC1 PC2 PC3 PC4 PC5 PC6 PC7 GPIO Port B and UART1 Receive Data Input GPIO Port B and UART3 Transmit Data Out GPIO Port B and UART3 Receive Data In GPIO Port B and UART3 Clear to Send GPIO Port B and UART3 Data Carrier Detect GPIO Port B and UART3 Data Set Ready GPIO Port B and Battery Monitor Interface GPIO Port C and UART1 Transmit Data Output GPIO Port C GPIO Port C GPIO Port C GPIO Port C GPIO Port C GPIO Port C GPIO Port C 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 16 mA 16 mA 16 mA 16 mA 16 mA 16 mA 16 mA 16 mA GPIO Port A 8 mA Asynchronous Memory Output Enable Asynchronous Memory Write Enable 0 Asynchronous Memory Controller Wait Clock Enable 3 for Synchronous Memory Synchronous Memory Clock2 Clock Enable 1 for Synchronous Memory Clock Enable 0 for Synchronous Memory Synchronous Memory Chip Select 0 Synchronous Memory Chip Select 1 Synchronous Memory Chip Select 2 Synchronous Memory Chip Select 3 Synchronous Memory Write Enable GPIO Port A and LCD data pins 16 and 17 16 mA 24 mA 16 mA 16 mA 16 mA 16 mA 16 mA 16 mA 16 mA 8 mA 16 mA 16 mA Address Bus 16 mA DESCRIPTION Address Bus and Synchronous Bank 0 Address Bus and Synchronous Bank 1 OUTPUT DRIVE 16 mA 16 mA 6 Advance Data Sheet 32-Bit System-on-Chip LH7A404 Table 1. Functional Pin List (Cont'd) BGA SIGNAL DESCRIPTION OUTPUT DRIVE AB10 PD0/LCDVD8 AA10 PD1/LCDVD9 Y10 PD2/LCDVD10 GPIO Port D and LCD Video Data Interface 16 mA W10 PD3/LCDVD11 AB11 PD4/LCDVD12 AA11 PD5/LCDVD13 Y11 AA8 AA9 Y9 W9 C4 A3 B3 A2 L13 K13 L12 K12 J12 K11 C10 A9 W4 AA1 AA2 AB1 AB2 AA3 AB3 Y3 AB4 AA4 Y4 AB5 AA5 W5 AB6 Y6 U3 V1 U4 V2 V3 V4 W1 PD6/LCDVD14 PE0/LCDVD4 PE1/LCDVD5 PE2/LCDVD6 PE3/LCDVD7 PE4 PE5 PE6 PE7 PF0 PF1 PF2 PF3 PF4 PF5/SCIDETECT PF6 PF7 PG0/nCFOE PG1/nCFWE PG2/nCFIORD PG3/nCFIOWR PG4/nCFREG PG5/nCFCE1 PG6/nCFCE2 PG7/PCDIR PH0/CFRESETA PH1/CFA8/CFA24/ CFRESETB PH2/nCFENA PH4/nCFWAIT/nCFWAITA PH5/CFA10/nCFWAITB PH6/AC97RESET PH7/nCFSTATEN LCDFP/LCDSPS LCDLP/LCDHRLP LCDCLS LCDSPL LCDUBL LCDSPR LCDLBR AB12 PD7/LCDVD15 GPIO Port E and LCD Video Data Interface 16 mA GPIO Port E 16 mA GPIO Port F and Smart Card Interface. Can be used for external interrupts. Interrupts can be level or edge triggered and are internally debounced. 8 mA GPIO Port G/Compact Flash Output Enable GPIO Port G/Compact Flash Write Enable GPIO Port G/Compact Flash I/O read strobe GPIO Port G/Compact Flash I/O write strobe GPIO Port G/Compact Flash Register memory access GPIO Port G/Compact Flash Chip Enable 1 GPIO Port G/Compact Flash Chip Enable 2 GPIO Port G/PC Card Direction GPIO Port H/Compact Flash Reset A GPIO Port H/Compact Flash Address Bit 8/PCMCIA1 Address Bit 24/PCMCIA2 Reset B GPIO Port H/Compact Flash Enable A GPIO Port H/Compact Flash WAIT Signal/PCMCIA WAIT A GPIO Port H/Compact Flash Address Bit 10/PCMCIA2 WAIT B GPIO Port H/AC97 reset GPIO Port H/Compact Flash Status Read Enable LCD Frame Pulse / HR-TFT Reset Row Driver Counter LCD Linepulse / HR-TFT Latch Pulse HR-TFT Clock for Row Drivers HR-TFT Start Pulse Left for reverse scanning HR-TFT Up, Down signal for reverse scanning HR-TFT Start Pulse Right for normal scanning HR-TFT Output for reverse scanning 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 16 mA 16 mA 16 mA 16 mA 16 mA 16 mA 16 mA PH3/CFA9/CFA25/nCFENB GPIO Port H/Compact Flash Address Bit 9/PCMCIA1 Address Bit 25/PCMCIA2 Enable B Advance Data Sheet 7 LH7A404 32-Bit System-on-Chip Table 1. Functional Pin List (Cont'd) BGA W2 W3 Y1 Y2 W6 AA7 Y7 W7 AB8 P10 AB9 Y18 LCDMOD LCDPS LCDCLPOWER LCDREV LCDCLKIN LCDVD0 LCDVD1 LCDVD2 LCDVD3 LCDM LCDDCLK USBDP AC bias for LCD. This signal is used on STN displays LCD Pixel Clock USB Device control USB Data Positive (Differential Pair) USB Data Negative (Differential Pair) USB Data Host Positive 0 (Differential Pair) USB Data Host Negative 0 (Differential Pair) USB Data Host Positive 1(Differential Pair) USB Data Host Negative 1(Differential Pair) USB Host Power USB Overcurrent DC-DC Converter 0 Enable DC-DC Converter 1 Enable DC-DC Converter 0 Output (Pulse Width Modulated) DC-DC Converter 1 Output (Pulse Width Modulated) PWM Output 2 PWM Output 3 PWM Synchronizing Input AC97 Codec Clock (AAC/Normal) AC97 Codec Output (AAC/Normal) AC97 Codec Sync (AAC/Normal) AC97 Codec Input (AAC/Normal) MultiMediaCard Clock (20 MHz MAX.)/optional SPI Mode Clock MultiMediaCard Command/optional SPI mode Data In MultiMediaCard Data/optional SPI mode Data Out MultiMediaCard Data 1 MultiMediaCard Data 2 MultiMediaCard Data 3 UART2 Clear to Send Signal UART2 Data Carrier Detect Signal UART2 Data Send Ready Signal UART1 Transmit / IrDA Transmit UART1 Receive / IrDA Receive UART2 Transmit Data Output UART2 Receive Data Input Synchronous Serial Port Clock Synchronous Serial Port Receive Synchronous Serial Port Transmit Synchronous Serial Port Frame Sync 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 16 mA 16 mA LCD Video Data Interface 16 mA SIGNAL DESCRIPTION HR-TFT MOD Signal used by the row driver HR-TFT Power Save HR-TFT Power Sequence Control HR-TFT Reverse External Clock Input for LCD controller OUTPUT DRIVE 16 mA 16 mA 16 mA 16 mA W17 USBDCP W18 USBDN AB19 USBHDP0 AA19 USBHDN0 AB20 USBHDP1 AA20 USBHDN1 Y19 B12 D12 A11 B11 C11 D11 A10 B9 C9 D9 A8 B8 D8 A7 B7 C7 A6 F4 E2 K10 F2 F1 G4 G3 K1 L2 L1 M4 USBHPWR PWMEN0 PWMEN1 PWM0 PWM1 PWM2 PWM3 PWMSYNC0 AC97CLK AC97OUT AC97SYNC AC97IN MMCCLK/SPICLK MMCCMD/SPIDI MMCDATA0/SPIDO MMCDATA1 MMCDATA2 MMCDATA3 UARTCTS2 UARTDCD2 UARTDSR2 UARTTX1/UARTIRTX1 UARTRX1/UARTIRRX1 UARTTXD2 UARTRXD2 SSPCLK SSPRX SSPTX SSPFRM AB21 USBHOVRCURR 8 Advance Data Sheet 32-Bit System-on-Chip LH7A404 Table 1. Functional Pin List (Cont'd) BGA H2 H1 J4 J3 J2 J1 K4 K2 B1 B2 C1 C3 D1 D2 G1 H3 L9 AB7 Y8 COL0 COL1 COL2 COL3 COL4 COL5 COL6 COL7 TCLK TDO TMST MEDCHG BATOK nBATCHG KMIDAT KMICLK BUZ nBLE2 nBLE1 JTAG Clock. This signal should be pulled-up to VDD JTAG Data Out JTAG Test Mode Select. This signal should be pulled-up to VDD Media Change for Smart Card interface Battery OK Battery Change Keyboard / Mouse data Keyboard /Mouse clock Buzzer Output (254 kHz MAX.) Byte Lane Enable 2 Byte Lane Enable 1 Battery Control for A/D controller battery monitor. Boot Width Pins. Used with the MEDCHG bit. On power up, the values on these pins are latched to determine the width and type of Boot device. Boot width can be 8-, 16-, or 32-bit. Touch Screen Controller Lower Right Y-minus A/D channel 1 A/D channel 6 Touch Screen Controller Lower Left Y-plus A/D channel 5 A/D channel 2 Touch Screen Controller Upper Right X-minus A/D channel 4 A/D channel 3 Touch Screen Controller Upper Left X-plus, Test Pins. Tie to VDD. Oscillator Enable Output Column Address Strobe Signal Row Address Strobe Signal Byte Lane Enable 3 Byte Lane Enable 0 8 mA 16 mA 16 mA 8 mA 8 mA 16 mA 16 mA 8 mA 16 mA 16 mA 16 mA 4 mA Keyboard Interface 8 mA SIGNAL DESCRIPTION OUTPUT DRIVE AA12 BATCNTL N11 N12 BOOTWIDTH0 BOOTWIDTH1 W12 LR_YM AA13 AN1 Y13 AN6 W13 LL_YP AB14 AN5 AA14 AN2 Y14 UR_XM W14 AN4 AB15 AN3 Y15 Y17 C18 D17 A15 B15 C15 D15 A14 B14 B13 C13 D13 A12 UL_XP nTEST1 nCAS nRAS nBLE3 nBLE0 DQM0 DQM1 DQM2 DQM3 SCIIO SCICLK SCIRESET SCIVCCEN W16 nTEST0 AA22 OSCEN Data Mask for synchronous memories 16 mA Smart Card Interface I/O Smart Card Interface Clock Smart Card Interface Reset Smart Card Interface VCC Enable 16 mA 16 mA 16 mA 16 mA Advance Data Sheet 9 LH7A404 32-Bit System-on-Chip Table 1. Functional Pin List (Cont'd) BGA B6 C6 D6 A5 C5 D5 A4 B4 CTCLKIN nRESETOUT DREQ0 DACK0 DEOT0 DREQ1 DACK1 DEOT1 SIGNAL Counter Timer Clock Input Reset Output to external devices DMA Request 0 DMA Acknowledge 0 DMA End Of Transfer 0 DMA Request 1 DMA Acknowledge 1 DMA End Of Transfer 1 16 mA 16 mA 16 mA 16 mA 16 mA DESCRIPTION OUTPUT DRIVE NOTES: 1. Signals beginning with `n' are Active LOW. 2. The SCLK pin can source up to 16 mA and sink up to 24 mA. See `DC Characteristics'. Table 2. LCD Pin Muxing PIN ASSIGNED DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 NOTES: 1. The Intensity bit is identically generated for all three colors. 2. MU = Monochrome Upper 3. CU = Color Upper 4. CL = Color Lower 4-BIT MONO STN SINGLE PANEL MUSTN3 MUSTN2 MUSTN1 MUSTN0 8-BIT MONO STN SINGLE PANEL MUSTN7 MUSTN6 MUSTN5 MUSTN4 MUSTN3 MUSTN2 MUSTN1 MUSTN0 COLOR STN SINGLE PANEL CUSTN7 CUSTN6 CUSTN5 CUSTN4 CUSTN3 CUSTN2 CUSTN1 CUSTN0 COLOR STN DUAL PANEL CUSTN7 CUSTN6 CUSTN5 CUSTN4 CUSTN3 CUSTN2 CUSTN1 CUSTN0 CLSTN7 CLSTN6 CLSTN5 CLSTN4 CLSTN3 CLSTN2 CLSTN1 CLSTN0 16-BIT TFT RED0 RED1 RED2 RED3 RED4 GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 Intensity 10 Advance Data Sheet 32-Bit System-on-Chip LH7A404 Table 3. Detailed Pin List BGA J9 K9 M9 N9 P9 P11 P12 P13 P14 N14 M14 L14 K14 J14 J13 J11 J10 E4 H4 L4 R4 W8 W11 W15 W19 T19 P19 M19 K19 G19 D18 D14 D10 D7 K3 Y5 Y12 V20 N20 H20 D20 C12 C8 F3 VDDC Core Power VSS I/O Ring Ground VDD I/O Ring Power SIGNAL RESET STATE STANDBY STATE PULL UP SCHMITT I/O SLEW RATE OUTPUT DRIVE Advance Data Sheet 11 LH7A404 32-Bit System-on-Chip Table 3. Detailed Pin List (Cont'd) BGA G2 M2 AA6 AA15 P21 K21 F21 B17 B10 B5 AA17 VDDA1 AB17 VSSA1 AA18 VDDA2 AB18 VSSA2 AB16 VDDA3 AB13 VSSA3 A1 B1 B2 C1 D3 C2 C3 D1 D2 E3 D4 F4 E2 E1 K10 F2 F1 G4 G3 G1 H3 TDI TCLK TDO TMST nPOR nEXTPWR MEDCHG BATOK nBATCHG nURESET WAKEUP UARTCTS2 UARTDCD2 nPWRFL UARTDSR2 UARTTX1/UARTIRTX1 UARTRX1/UARTIRRX1 UARTTXD2 UARTRXD2 KMIDAT KMICLK Analog Power for PLL1 Analog Ground for PLL1 Analog Power for PLL2 Analog Ground for PLL2 Analog Power for TSC Analog Ground for TSC Input Input LOW Input Input Input Input Input Input Input Input Input Input Input Input LOW Input LOW Input Input Input Input Input No Change No Change Input Input Input Input Input Input Input Input Input Input Input No Change Input No Change Input No Change No Change Ext Ext Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes I I O I I I I I I I I I/O I/O I I/O I/O I/O I/O I/O I/O I/O 110 mA/ns 110 mA/ns 110 mA/ns 110 mA/ns 110 mA/ns 95 mA/ns 95 mA/ns 8 mA 8 mA 8 mA 8 mA 8 mA 16 mA 16 mA 110 mA/ns 110 mA/ns 8 mA 8 mA 100 mA/ns 4 mA VSSC Core Ground SIGNAL RESET STATE STANDBY STATE PULL UP SCHMITT I/O SLEW RATE OUTPUT DRIVE 12 Advance Data Sheet 32-Bit System-on-Chip LH7A404 Table 3. Detailed Pin List (Cont'd) BGA H2 H1 J4 J3 J2 J1 K4 K2 L9 K1 L3 L2 L1 M4 M3 M1 N4 N3 N2 N1 P4 P3 P2 L10 L11 M10 M11 N10 P1 R1 R2 R3 T1 T2 T3 T4 U1 U2 U3 U4 V1 V2 V3 COL0 COL1 COL2 COL3 COL4 COL5 COL6 COL7 BUZ SSPCLK PGMCLK SSPRX SSPTX SSPFRM PA0/LCDVD16 PA1/LCDVD17 PA2 PA3 PA4 PA5 PA6 PA7 PB0/UARTRXD1 PB1/UARTTXD3 PB2/UARTRXD3 PB3/UARTCTS3 PB4/UARTDCD3 PB5/UARTDSR3 PB6/BMISWIB/BMISMBIO PB7/BMISMBCLK PC0/TXD1 PC1 PC2 PC3 PC4 PC5 PC6 PC7 LCDFP/LCDSPS LCDCLS LCDLP/LCDHRLP LCDSPL LCDUBL LOW LOW LOW LOW LOW LOW when not in HR-TFT mode No Change LOW when not in HR-TFT mode No Change No Change I/O I/O I/O I/O I/O 95 mA/ns 95 mA/ns 95 mA/ns 95 mA/ns 95 mA/ns 16 mA 16 mA 16 mA 16 mA 16 mA LOW No Change I/O 95 mA/ns 16 mA Input Input Input Input Input Input Input LOW No Change LOW if UART3 enabled else No Change No Change No Change No Change No Change Input if SMB enabled else No Change No Change I/O 95 mA/ns 16 mA I/O I/O I/O I/O I/O I/O 110 mA/ns 110 mA/ns 110 mA/ns 110 mA/ns 110 mA/ns 110 mA/ns 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA GPIO Port A No Change I/O 110 mA/ns 8 mA LOW LOW LOW Input Input HIGH Input LOW LOW LOW LOW LOW Input No Change I/O I/O I/O I/O I/O I/O I/O 110 mA/ns 110 mA/ns 110 mA/ns 110 mA/ns 110 mA/ns 110 mA/ns 110 mA/ns 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA HIGH HIGH HIGH I/O 100 mA/ns 8 mA SIGNAL RESET STATE STANDBY STATE PULL UP SCHMITT I/O SLEW RATE OUTPUT DRIVE Advance Data Sheet 13 LH7A404 32-Bit System-on-Chip Table 3. Detailed Pin List (Cont'd) BGA V4 W1 W2 W3 Y1 Y2 W4 AA1 AA2 AB1 AB2 AA3 AB3 Y3 AB4 AA4 Y4 AB5 AA5 W5 AB6 Y6 W6 AB7 AA7 Y7 W7 AB8 AA8 Y8 P10 AB9 AA9 Y9 W9 LCDSPR LCDLBR LCDMOD LCDPS LCDCLPOWER LCDREV PG0/nCFOE PG1/nCFWE PG2/nCFIORD PG3/nCFIOWR PG4/nCFREG PG5/nCFCE1 PG6/nCFCE2 PG7/PCDIR PH0/CFRESETA PH1/CFA8/CFA24/ CFRESETB PH2/nCFENA PH3/CFA9/CFA25/nCFENB Input PH4/nCFWAIT/nCFWAITA PH5/CFA10/nCFWAITB PH6/AC97RESET PH7/nCFSTATEN LCDCLKIN nBLE2 LCDVD0 LCDVD1 LCDVD2 LCDVD3 PE0/LCDVD4 nBLE1 LCDM LCDDCLK PE1/LCDVD5 PE2/LCDVD6 PE3/LCDVD7 Input LOW if 8 bit LCD enabled else No Change I/O 95 mA/ns 16 mA Input HIGH LOW LOW LOW if 8 bit LCD enabled else No Change HIGH LOW LOW I/O I/O I/O I/O 95 mA/ns 95 mA/ns 95 mA/ns 95 mA/ns 16 mA 16 mA 16 mA 16 mA LOW LOW I/O 95 mA/ns 16 mA Input HIGH No Change HIGH I I/O 95 mA/ns 16 mA No Change I/O 110 mA/ns 8 mA LOW No Change I/O 110 mA/ns 8 mA SIGNAL RESET STATE LOW HIGH HIGH HIGH LOW HIGH STANDBY STATE No Change No Change No Change No Change No Change No Change PULL UP SCHMITT I/O I/O I/O I/O I/O I/O I/O SLEW RATE 95 mA/ns 95 mA/ns 95 mA/ns 95 mA/ns 95 mA/ns 95 mA/ns OUTPUT DRIVE 16 mA 16 mA 16 mA 16 mA 16 mA 16 mA AB10 PD0/LCDVD8 AA10 PD1/LCDVD9 Y10 PD2/LCDVD10 LOW LOW if Dual Panel LCD else No Change I/O 95 mA/ns 16 mA W10 PD3/LCDVD11 AB11 PD4/LCDVD12 AA11 PD5/LCDVD13 Y11 PD6/LCDVD14 AB12 PD7/LCDVD15 14 Advance Data Sheet 32-Bit System-on-Chip LH7A404 Table 3. Detailed Pin List (Cont'd) BGA SIGNAL RESET STATE Input Input N12 BOOTWIDTH1 W12 LR_YM AA13 AN1 Y13 AN6 STANDBY STATE No Change Input Yes PULL UP SCHMITT I/O I/O I SLEW RATE 95 mA/ns OUTPUT DRIVE 16 mA AA12 BATCNTL N11 BOOTWIDTH0 W13 LL_YP AB14 AN5 AA14 AN2 Y14 UR_XM A/D Inputs A/D Inputs W14 AN4 AB15 AN3 Y15 UL_XP Oscilator AA16 XTALIN Y16 XTALOUT W16 nTEST0 Y17 nTEST1 Input Input HIGH LOW HIGH LOW HIGH LOW HIGH Input HIGH Oscilator HIGH LOW HIGH HIGH HIGH HIGH Asynchronous Memory Controller Wait Input Input HIGH LOW HIGH LOW HIGH LOW HIGH No Change HIGH Yes I I W17 USBDCP Y18 USBDP Yes W18 USBDN AB19 USBHDP0 AA19 USBHDN0 AB20 USBHDP1 AA20 USBHDN1 Y19 USBHPWR I/O I/O I/O I/O O I I/O 95 mA/ns 16 mA 95 mA/ns 16 mA AB21 USBHOVRCURR AB22 nCS0 AA21 XTAL32IN Y20 N13 XTAL32OUT nCS1 HIGH LOW HIGH HIGH No Change No Change I/O I/O I/O I/O I/O I/O I/O 95 mA/ns 110 mA/ns 95 mA/ns 95 mA/ns 95 mA/ns 95 mA/ns 95 mA/ns 16 mA 8 mA 16 mA 16 mA 16 mA 16 mA AA22 OSCEN Y21 nCS2 W20 nCS3/nMMCSEL Y22 nCS6 W21 nCS7 M13 nWAIT Advance Data Sheet 15 LH7A404 32-Bit System-on-Chip Table 3. Detailed Pin List (Cont'd) BGA W22 D0 v21 U22 U20 T22 T20 R21 R19 P20 N21 M22 M20 L21 L19 K20 J21 J19 H21 G22 G20 F20 E22 E20 D22 C22 B22 B21 D19 B20 A20 B19 B18 V22 V19 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 A0 A1 HIGH HIGH I/O 95 mA/ns 16 mA LOW LOW I/O 95 mA/ns 16 mA SIGNAL RESET STATE STANDBY STATE PULL UP SCHMITT I/O SLEW RATE OUTPUT DRIVE 16 Advance Data Sheet 32-Bit System-on-Chip LH7A404 Table 3. Detailed Pin List (Cont'd) BGA U21 U19 T21 R22 R20 P22 N22 N19 M21 L22 L20 K22 J22 J20 H22 H19 G21 F22 F19 E21 E19 D21 C21 A18 A17 C17 A22 C20 A21 C19 A19 C18 D17 A16 B16 C16 D16 A15 B15 C15 D15 A14 B14 C14 A13 A2/SA0 A3/SA1 A4/SA2 A5/SA3 A6/SA4 A7/SA5 A8/SA6 A9/SA7 A10/SA8 A11/SA9 A12/SA10 A13/SA11 A14/SA12 A15/SA13 A16/SBANK0 A17/SBANK1 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 nSCS0 nSCS1 nSCS2 nSCS3 nSWE nCAS nRAS SCKEN3 SCLK SCKE12 SCKE0 nBLE3 nBLE0 DQM0 DQM1 DQM2 DQM3 nOE nWE0 HIGH HIGH HIGH HIGH I/O I/O 95 mA/ns 95 mA/ns 16 mA 16 mA Data Mask for Synchronous Memories I/O 95 mA/ns 16 mA HIGH HIGH HIGH Depends on MEDCHG LOW HIGH HIGH HIGH HIGH HIGH HIGH HIGH LOW No Change No Change No Change No Change No Change I/O I/O I/O I/O I/O I/O I/O I/O I/O 95 mA/ns 95 mA/ns 95 mA/ns 95 mA/ns 190 mA/ns 95 mA/ns 95 mA/ns 110 mA/ns 110 mA/ns 16 mA 16 mA 16 mA 16 mA 24 mA 16 mA 16 mA 8 mA 8 mA HIGH HIGH I/O 95 mA/ns 16 mA LOW LOW 95 mA/ns 16 mA SIGNAL RESET STATE STANDBY STATE PULL UP SCHMITT I/O SLEW RATE OUTPUT DRIVE Advance Data Sheet 17 LH7A404 32-Bit System-on-Chip Table 3. Detailed Pin List (Cont'd) BGA B13 C13 D13 A12 B12 D12 A11 B11 C11 D11 A10 L13 K13 L12 K12 J12 K11 C10 A9 B9 C9 D9 A8 B8 D8 A7 B7 C7 A6 B6 C6 D6 A5 C5 D5 A4 B4 C4 A3 B3 A2 SCIIO SCICLK SCIRESET SCIVCCEN PWMEN0 PWMEN1 PWM0 PWM1 PWM2 PWM3 PWMSYNC0 PF0 PF1 PF2 PF3 PF4 PF5/SCIDETECT PF6 PF7 AC97CLK AC97OUT AC97SYNC AC97IN MMCCLK/SPICLK MMCCMD/SPIDI MMCDATA0/SPIDO MMCDATA1 MMCDATA2 MMCDATA3 CTCLKIN nRESETOUT DREQ0 DACK0 DEOT0 DREQ1 DACK1 DEOT1 PE4 PE5 PE6 PE7 Input Input I/O 95 mA/ns 16 mA Input LOW LOW Input LOW Input Input Input Input Input Input LOW Input Input Input Input Input Input Input LOW LOW Input LOW Input Input Input Input Input No Change HIGH No Change No Change No Change No Change No Change No Change I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I O I I/O I/O I I/O I/O 95 mA/ns 95 mA/ns 16 mA 16 mA 95 mA/ns 95 mA/ns 16 mA 16 mA 95 mA/ns 16 mA 110 mA/ns 110 mA/ns 110 mA/ns 110 mA/ns 110 mA/ns 110 mA/ns 110 mA/ns 110 mA/ns 110 mA/ns 110 mA/ns 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA Input No Change I/O 110 mA/ns 8 mA SIGNAL RESET STATE Input Input Input LOW HIGH/LOW HIGH/LOW Input Input Input Input Input STANDBY STATE LOW LOW LOW No Change HIGH/LOW HIGH/LOW No Change No Change No Change No Change No Change PULL UP SCHMITT I/O I/O I/O I/O O I/O I/O I/O I/O I/O I/O I/O SLEW RATE 95 mA/ns 95 mA/ns 95 mA/ns 95 mA/ns 110 mA/ns 110 mA/ns 110 mA/ns 110 mA/ns 110 mA/ns 110 mA/ns 110 mA/ns OUTPUT DRIVE 16 mA 16 mA 16 mA 16 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA NOTE: `No Change' means the pin remains as it was programmed prior to entering the Standby state. 18 Advance Data Sheet 32-Bit System-on-Chip LH7A404 TOUCH SCREEN CONTR. ROM FLASH 1 4 7 2 5 8 0 3 6 9 # * SMART CARD STN/TFT/ HR-TFT SSP UART SCI MULTIMEDIA CARD SRAM GPIO MMC/SD SDRAM LH7A404 COMPACT FLASH DMA CODEC AC97 PC CARD PCMCIA IR DEVICE HOST USB HOST BATTERY BMI DC to DC VOLTAGE GENERATION CIRCUITRY LH7A404-2 Figure 2. Application Diagram SYSTEM DESCRIPTIONS ARM922T Processor The LH7A404 microcontroller features the ARM922T cached core with an Advanced High-performance Bus (AHB) interface. The processor is a member of the ARM9T family of processors. For more information, see the ARM document, `ARM922T Technical Reference Manual', available on ARM's website at www.arm.com. The 32.768 kHz clock provides the source for the Real Time Clock tree and power-down logic. This clock is used for the power state control and is the only clock in the LH7A404 that runs continuously. The 32.768 kHz clock is divided down to 1 Hz for the Real Time Clock counter using a ripple divider to save power. The 14.7456 MHz source is used to generate the main system clocks for the LH7A404. It is the source for PLL1 and PLL2, the primary clock for the peripherals, and the source clock to the programmable clock (PGM) divider. PLL1 provides the main clock tree for the chip. It generates the following clocks: FCLK, HCLK, and PCLK. FCLK is the clock that drives the ARM922T core. HCLK is the main bus (AHB) clock, as such it clocks all memory interfaces, bus arbitrators and the AHB peripherals. HCLK is generated by dividing FCLK by 1, 2, 3, or 4. HCLK can be gated by the system to enable low power operation. PCLK is the peripheral bus (APB) clock. It is generated by dividing HCLK by either 2, 4, or 8. PLL2 generates a fixed 48 MHz clock signal for the USB peripheral. Clock and State Controller The clocking scheme in the LH7A404 is based around two primary oscillator inputs. These are the 14.7456 MHz input crystal and the 32.768 kHz real time clock oscillator; see Figure 3. The 14.7456 MHz oscillator supplies the main system clock domains for the LH7A404. The 32.768 kHz oscillator controls the power-down operations and real time clock peripheral. The clock and state controller provides the clock gating and frequency division necessary, and then supplies the clocks to the processor and rest of the system. The amount of clock gating that actually takes place depends on the power saving mode selected. Advance Data Sheet 19 LH7A404 32-Bit System-on-Chip Power Modes The LH7A404 has three operational states: Run, Halt, and Standby. During Run all clocks are hardware enabled and the processor is clocked. In the Halt mode the device is functioning, but the processor clock is halted while it waits for an event such as a key press. Standby equates to the computer being switched `off', i.e. no display (LCD disabled) and the main oscillator is shut down. Data Paths The data paths in the LH7A404 are: * The AMBA AHB bus * The AMBA APB bus * The External Bus Interface * The LCD AHB bus * The DMA busses. AMBA AHB BUS The Advanced Microprocessor Bus Architecture AHB (AMBA AHB) is a high speed 32-bit-wide data bus. The AMBA AHB is for high-performance, high-clock-frequency system modules. Peripherals with high bandwidth requirements are connected to the LH7A404 core processor using the AHB bus, Boot ROM, Vectored Interrupt Controllers, and USB Device. These include the external and internal memory interfaces, the LCD registers, palette RAM and the bridge to the Advanced Peripheral Bus (APB) interface. The APB Bridge transparently converts the AHB access into the slower speed APB accesses. All control registers for the APB peripherals are programmed using the AHB-to-APB bridge interface. The main AHB data and address lines are configured using a multiplexed bus. This removes the need for tri-state buffers and bus holders and simplifies bus arbitration. Reset Modes Three external signals can generate resets to the LH7A404: nPOR (power on reset), nPWRFL (power failure) and nURESET (user reset). If any of these are active, a system reset is internally generated. An nPOR reset performs a full system reset. The nPWRFL and nURESET resets perform a full system reset except for the SDRAM refresh control, SDRAM Global Configuration, SDRAM Device Configuration, and the RTC peripheral registers. The SDRAM controller issues a self-refresh command to external SDRAM before the system enters an nPWRFL and nURESET reset. This allows the system to maintain its Real Time Clock and SDRAM contents. At reset termination, the chip enters Standby mode. Once in the Run mode the PWRSR register can be interrogated to determine the nature of the reset and the trigger source, after which software can then take appropriate actions. 14.7456 MHz MAIN OSC. 32.768 kHz RTC OSC. FCLK STATE CONTROLLER HCLK (TO PROCESSOR CORE) DIVIDE REGISTER HCLK /2, /4, /8 PCLKs LH7A404-6 Figure 3. Clock and State Controller Block Diagram 20 Advance Data Sheet 32-Bit System-on-Chip LH7A404 AMBA APB BUS The AMBA APB bus is a low speed 32-bit-wide peripheral data bus. The speed of the APB bus is selected by dividing the clock speed of the AHB bus by two, four, or eight. EXTERNAL BUS INTERFACE (EBI) The External Bus Interface (EBI) provides a 32-bit wide, high speed gateway to external memory devices. The supported memory devices include: * Asynchronous RAM/ROM/Flash * Synchronous DRAM/Flash * PCMCIA interfaces * Compact Flash interfaces. The EBI can be controlled by either the Asynchronous Memory Controller or Synchronous Memory Controller. There is an arbiter on the EBI input, with priority given to the Synchronous Memory Controller interface. LCD BUS The LCD controller has its own local memory bus that connects it to the system's embedded memory and external SDRAM. The function of this local data bus is to allow the LCD controller to perform its video refresh function without congesting the main AHB bus. This leads to better system performance and lower power consumption. There is an arbiter on both the embedded memory and the synchronous memory controller. In both cases the LCD bus is given priority. DMA BUSES The LH7A404 has a DMA system which connects the higher speed/higher data volume APB peripherals (MMC, USB and AC97) to the AHB bus. This enables the efficient transfer of data between these peripherals and external memory without the intervention of the ARM922T core. The DMA engine does not support memory-to-memory transfers. USB HOST CONTROLLER DMA BUS The USB Host Controller has its own DMA controller. It acts as another bus master on the AHB bus. It does not interact with the non-USB DMA controller except in bus arbritration. Memory Map The LH7A404 system has a 32-bit-wide address bus, allowing addressing up to 4GB of memory. This memory space is subdivided into a number of memory banks, shown in Figure 4. Four of these banks (each 256MB) are allocated to the Synchronous Memory Controller. Eight banks (each 256MB) are allocated to the Asynchronous Memory Controller. Two of these eight banks are designed for PCMCIA systems. Part of the remaining memory space is allocated to the embedded SRAM, and to the control registers of the AHB and APB. The rest of the memory space is not used. The LH7A404 can boot from either synchronous or asynchronous ROM/Flash. The selection is determined by the value of the MEDCHG pin at power-on reset as shown in Table 4. When booting from synchronous memory, bank 4 (nSCS3) is mapped into memory location zero. When booting from asynchronous memory, memory bank 0 (nSCS0) is mapped into memory location zero. Figure 4 shows the memory map of the LH7A404 system for the two boot modes. Once the LH7A404 has booted, the boot code can configure the ARM922T MMU to remap the low memory space to a location in RAM. This allows the user to set the interrupt vector table. Table 4. Boot Modes BOOT MODES 8-bit ROM 16-bit ROM 32-bit ROM 32-bit ROM 16-bit SFlash (Initializes Mode Register) 16-bit SROM (Initializes Mode Register) 32-bit SFlash (Initializes Mode Register) 32-bit SROM (Initializes Mode Register) LATCHED BOOTWIDTH1 0 0 1 1 0 0 1 1 LATCHED BOOTWIDTH0 0 1 0 1 0 1 0 1 LATCHED MEDCHG 0 0 0 0 1 1 1 1 Advance Data Sheet 21 LH7A404 32-Bit System-on-Chip ASYNC. MEM (nCS0) F000.0000 E000.0000 D000.0000 C000.0000 B001.4000 B000.0000 8000.3800 8000.2000 8000.0000 7000.0000 6000.0000 5000.0000 4000.0000 3000.0000 2000.0000 1000.0000 0000.0000 SYNC. MEMORY BOOT SYNC. MEM (nSDCE2) SYNC. MEM (nSDCE1) SYNC. MEM (nSDCE0) NOT USED EMBEDDED SRAM NOT USED AHB INTERNAL REGISTERS APB INTERNAL REGISTERS ASYNC. MEM (nCS7) ASYNC. MEM (nCS6) PCMCIA (SLOT1) PCMCIA (SLOT0) ASYNC. MEM (nCS3) ASYNC. MEM (nCS2) ASYNC. MEM (nCS1) SYNC. ROM (nSDCE3) SYNC. MEM (nSDCE3) SYNC. MEM (nSDCE2) SYNC. MEM (nSDCE1) SYNC. MEM (nSDCE0) NOT USED EMBEDDED SRAM NOT USED AHB INTERNAL REGISTERS APB INTERNAL REGISTERS ASYNC. MEM (nCS7) ASYNC. MEM (nCS6) PCMCIA (SLOT1) PCMCIA (SLOT0) ASYNC. MEM (nCS3) ASYNC. MEM (nCS2) ASYNC. MEM (nCS1) ASYNC. ROM (nSDCE0) ASYNC. MEMORY BOOT 256MB 256MB 256MB 256 MB 80KB 256MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB LH7A404-7 Figure 4. Memory Mapping for Each Boot Mode 22 Advance Data Sheet 32-Bit System-on-Chip LH7A404 Vectored Interrupt Controller (VIC) The LH7A404 VIC controls the interrupts of up to 32 different sources. Two VICs are daisy-chained together to support up to 64 different interrupts. The VIC supports both FIQ and IRQ interrupts. FIQ interrupts have a higher priority than IRQ interrupts. Each VIC can support up to 16 vectored interrupts, for a total of 32 vectored interrupts. If two interrupts with the same priority become active at the same time, the priority must be resolved in software. When an interrupt becomes active, the VIC generates an FIQ or IRQ if the corresponding mask bit is set. No latching of interrupts takes place in the VIC. After a power-on reset, all mask register bits are cleared, masking all interrupts. The mask bits must be set by software after power-on reset for any interrupts to be enabled. A vectored interrupt has improved latency as it provides direct information about where its service routine is located and eliminates software arbitration needed with a simple interrupt controller. The VICs continue to operate in Halt and Standby modes, so external interrupts may bring the chip out of these low power modes. External Bus Interface The ARM922T, LCD controller, and DMA engine have access to an external memory system. The LCD controller has access to an internal frame buffer in embedded SRAM and an extension buffer in Synchronous Memory for large displays. The processor and DMA engine share the main system bus, providing access to all external memory devices and the embedded SRAM frame buffer. An arbitration unit ensures that control over the External Bus Interface (EBI) is only granted when an existing access has been completed. See Figure 5. ASYNCHRONOUS MEMORY CONTROLLER SDRAM SRAM SYSTEM AHB BUS ARBITER ARM922T DMA CONTROLLER DATA EXTERNAL BUS INTERFACE ADDRESS/ (EBI) CONTROL SDRAM LCD CONTROLLER EMBEDDED SRAM 80KB SYNCHRONOUS BUS MEMORY ARBITER CONTROLLER ROM LCD MMU LCD AHB BUS LH7A404-8 Figure 5. External Bus Interface Block Diagram Advance Data Sheet 23 LH7A404 32-Bit System-on-Chip Embedded SRAM The LH7A404 incorporates 80KB of embedded SRAM. This embedded memory is used for storing code, data, or LCD frame data and is contiguous with external SDRAM. The 80KB is large enough to store a QVGA panel (320 x 240) at 8 bits per pixel, equivalent to 70KB of information. Locating the frame buffer on chip reduces the overall power consumed by any application that uses the LH7A404. Normally, the system performs external accesses to acquire this data. The LCD controller automatically uses an overflow frame buffer in SDRAM if a larger screen size is required. This overflow buffer can be located on any 4KB page boundary in SDRAM, allowing software to set the MMU (in the LCD controller) page tables such that the two memory areas appear contiguous. Byte, half-word and word accesses are permissible. SDRAM (Synchronous) Memory Controller The SDRAM (Synchronous) Memory Controller provides a high speed memory interface to a wide variety of synchronous memory devices, including Synchronous DRAM, Synchronous Flash and Synchronous ROMs. The key features of the controller are: * LCD DMA port for high bandwidth * Up to four Synchronous Memory banks can be independently set up * Includes special configuration bits for Synchronous ROM operation * Includes ability to program Synchronous Flash devices using write and erase commands * On booting from Synchronous ROM, (and optionally with Synchronous Flash), a configuration sequence is performed before releasing the processor from reset * Data is transferred between the controller and the Synchronous DRAM in four-word bursts. Longer transfers within the same page are concatenated, forming a seamless burst * Programmable for 16- or 32-bit data bus size * Two reset domains enable Synchronous DRAM contents to be preserved over a `soft' reset * Power saving Synchronous Memory SCKE and external clock modes provided. Static Memory Controller (SMC) The asynchronous Static Memory Controller (SMC) provides an interface between the AMBA AHB system bus and external (off-chip) memory devices. The SMC simultaneously supports up to eight independently configurable memory banks. Each memory bank can support: * SRAM * ROM * Flash EPROM * Burst ROM memory. Each memory bank may use devices using either 8-, 16-, or 32-bit external memory data paths. The memory controller can be configured to support either littleendian or big-endian operation. The memory banks can be configured to support: * Non-burst read and write accesses only to highspeed CMOS static RAM * Non-burst write accesses, nonburst read accesses and asynchronous page mode read accesses to fast-boot block flash memory. The SMC has six main functions: * * * * * * Memory bank select Access sequencing Wait state generation Byte lane write control External bus interface Compact Flash or PCMCIA interfacing. Secure Digital/MultiMediaCard (MMC) The SD Memory Card (Secure Digital Memory Card) is a flash-based memory card that meets the security, capacity, performance, and environment requirements inherent in electronic devices. The SD Memory Card host supports MultiMediaCard (MMC) operation as well and is forward compatible. The main difference between SD Card and MMC is the initialization process. The Secure Digital and MMC adapter can be used as an MMC card or as an SD card and supports the full MMC/SD bus protocol as defined in the MMC system specification 2.11 provided by the MMC Definition Group and the SD Memory Card Spec v1.0 from the SD group. The controller can also implement the SPI interface to the cards. SD/MMC INTERFACE DESCRIPTION The SD/MMC controller uses the three-wire serial data bus (clock, command, and data) to input and output data to and from the MMC card, and to configure and acquire status information from the card's registers. The SD differs only in that it has four data lines. 24 Advance Data Sheet 32-Bit System-on-Chip LH7A404 The SD/MMC bus lines can be divided into three groups: * Power supply: VSS1, VSS2 and VDD * Data transfer: MMCCMD, MMCDAT0, MMCDAT1, MMCDAT2, MMCDAT3 (for MMC, do not use MMCDAT1, MMCDAT2, MMCDAT3) * Clock: MMCCLK MMC bus lines can be divided into three groups: * Power supply: VDD and VSS * Data Transfer: MMCCMD, MMCDATA * Clock: MMCLK. MMC ADAPTER The MMC Adapter implements MMC specific functions, serves as the bus master for the MMC Bus and implements the standard interface to the MMC Cards (card initialization, CRC generation and validation, command/response transactions, etc.). PROGRAMMABLE PARAMETERS * Smart card clock frequency * Communication baud rate * Protocol convention * Card activation/deactivation time * Check for maximum time for first character of Answer to Reset (ATR) reception * Check for maximum duration of ATR character stream * Check for maximum time of receipt of first character of data stream * Check for maximum time allowed between characters * Character guard time * Block guard time * Transmit/receive character retry. Direct Memory Access Controller (DMA) The DMA Controller can be used to interface streams from 20 internal peripherals to the system memory using 10 fully-independent programmable channels which consist of five M2P (transmit) channels and five P2M (receive) channels. The following peripherals may be allocated to the 10 channels: * USB Device * USB Host * SD/MMC * AAC * UART1 * UART2 * UART3 Each of the above peripherals contain one Tx and one Rx channel, except the AAC, which contains three Tx and Rx channels. These peripherals also have their own bi-directional DMA bus, capable of simultaneously transferring data in both directions. All memory transfers take place via the main system AHB bus. The DMA Controller can also be used to interface streams from memory-to-memory (M2M) or memoryto-external peripheral (M2P) using two dedicated M2M channels. External handshake signals are available to suport memory-to-/from-external peripheral (M2P/ P2M) transfers. A software trigger is available for M2M transfers only. Smart Card Interface (SCI) The SCI (ISO7816) connects to an external Smart Card reader. The SCI can autonomously control data transfer to and from the smart card. Transmit and receive data FIFOs are provided to reduce the required interaction between the CPU core and the peripheral. SCI FEATURES * Supports asynchronous T0 and T1 transmission protocols * Supports clock rate conversion factor F = 372, with bit rate adjustment factors D = 1, 2, or 4 supported * Eight-character-deep buffered Tx and Rx paths * Direct interrupts for Tx and Rx FIFO level monitoring * Interrupt status register * Hardware-initiated card deactivation sequence on detection of card removal * Software-initiated card deactivation sequence on transaction complete * Limited support for synchronous smart cards via registered input/output. Advance Data Sheet 25 LH7A404 32-Bit System-on-Chip The DMA features: * Two dedicated channels for M2M and external M2P/ P2M * Ten fully independent, programmable DMA controller internal M2P/P2M channels (5 Tx and 5 Rx) * Channels assignable to one of a number of different peripherals * Independent source and destination address registers. Source and destination can be programmed to auto-increment or not auto-increment for M2M channels * Two buffer descriptors per M2P and M2M channel to avoid potential data under/over-flow due to software introduced latency. A buffer refers to the area in system memory that is characterized by a buffer descriptor, ie., a start address and the length of the buffer in bytes * No AMBA wrapping bursts for DMA channels; only incrementing bursts are supported * Buffer size independent of the peripheral's packet size for the internal M2P channels. Transfers can automatically switch between buffers * Maskable interrupt generation * Internal arbitration between DMA channels, plus support for an AHB bus arbiter * DMA data transfer sizes, byte, word and quad-word data transfers are supported using a 16-byte data bay. Maximum data transfer size per M2M channel is programmable * Per-channel clock gating reducing power in channels that have not been enabled by software. See the `Clock and State Controller' section. A set of control and status registers are available to the system processor for setting up DMA operations and monitoring their status. System interrupts are generated when any/all of the DMA channels wish to inform the processor to update the buffer descriptor. The DMA controller can service 10 out of 20 possible peripherals using the ten DMA channels, each with its own peripheral DMA bus capable of simultaneously transferring data in both directions. The SD/MMC, UART1/2/3, USB Device, and USB Host peripherals can each use two DMA channels, one for transmit and one for receive. The AAC peripheral can use six DMA channels (three transmit and three receive) to allow different sample frequency data queues to be handled with low software overheads. The DMA controller includes an M2M transfer feature allowing block moves of data from one memory address space to another with minimum of program effort and time. An M2M software trigger capability is provided. The DMA controller can also fill a block of memory with data from a single location. The DMA controller's M2M channels can also be used in M2P/P2M mode. A set of external handshake signals, DREQ, DACK and TC/DEOT are provided for each of two M2M channels. DREQ (input) can be programmed edge or level active, and active HIGH or LOW. The peripheral may hold DREQ active for the duration of the block transfers or may assert/deassert on each transfer. DACK (output) can be programmed active HIGH or LOW. DACK will assert and return to de-asserted with each Read or Write, the timing coinciding with nOE or nWE from the EBI. TC/DEOT is a bidirectional signal with programmable direction and active polarity. When configured as an Output, the DMA will assert Terminal Count (TC) on the final transfer to coincide with the DACK, typically when the byte count has expired. When configured as an Input, the peripheral must assert DEOT concurrent with DREQ for the final transfer in the block. Transfer is terminated when DEOT is asserted by the external peripheral or when the byte count expires, whichever occurs first. Status bits indicate if the actual byte count is equal to the programmed limit, and if the count was terminated by peripheral asserting DEOT. Terminating the transfer causes a DMA interrupt on that channel and rollover to the `other' buffer if so configured. For byte- or word-wide peripherals, the DMA is programmed to request byte- or word-wide AHB transfers respectively. The DMA does not issue an AHB HREQ for a transfer until it has DREQ asserted after a DACK for the previous transfer; and the previous transfer has been asserted for the duration of the programmed wait states in the SMC (and possibly DREQ is sampled in the cycle DACK is deasserted). USB Device The features of the USB are: * Fully compliant to USB 1.1 specification * Provides a high-level interface that shields the firmware from USB protocol details * Compatible with both OpenHCI and Intel UHCI standards * Supports full-speed (12 Mbps) functions * Supports Suspend and Resume signalling. 26 Advance Data Sheet 32-Bit System-on-Chip LH7A404 USB Host Controller The features of the USB Host Controller are: * Open Host Controller Interface Specification (OpenHCI) Rev. 1.0 compatible * Universal Serial Bus Specification Rev. 1.1 compatible * Support for both Low Speed and High Speed USB devices * Root Hub has two Downstream Ports * DMA functionality. * Support for up to 4 different codec sampling rates at a time with its 4 transmit and 4 receive channels. The transmit and receive paths are buffered with internal FIFO memories, allowing data to be stored independently in both transmit and receive modes. The outgoing data for the FIFOs can be written via either the APB interface or with DMA channels 1-3. Audio Codec Interface (ACI) The ACI provides: * A digital serial interface to an off-chip 8-bit codec * All the necessary clocks and timing pulses to perform serialization or de-serialization of the data stream to or from the codec device. The interface supports full duplex operation and the transmit and receive paths are buffered with internal FIFO memories allowing up to 16 bytes to be stored independently in both transmit and receive modes. The ACI includes a programmable frequency divider that generates a common transmit and receive bit clock output from the on-chip ACI clock input (ACICLK). Transmit data values are output synchronous with the rising edge of the bit clock output. Receive data values are sampled on the falling edge of the bit clock output. The start of a data frame is indicated by a synchronization output signal that is coincident with the bit clock. Color LCD Controller The LH7A404's LCD Controller is programmable to support up to 1,024 x 768, 16-bit color LCD panels. It interfaces directly to STN, color STN, TFT, and HR-TFT panels. Unlike other LCD controllers, the LH7A404's LCD Controller incorporates the timing conversion logic from TFT to HR-TFT, allowing a direct interface to HRTFT and minimizing external chip count. The Color LCD Controller features support for: * Up to 1,024 x 768 Resolution * 16-bit Video Bus * STN, Color STN, HR-TFT, TFT panels * Single and Dual Scan STN panels * Up to 15 Gray Shades * Up to 64 k-Colors Pulse Width Modulator (PWM) The Pulse Width Modulator features: * Configurable dual output * Separate input clocks for each PWM output * 16-bit resolution * Programmable synchronous mode support - Allows external input to start PWM * Programmable pulse width (duty cycle), interval (frequency), and polarity - Static programming: when the PWM is stopped - Dynamic programming: when the PWM is running - Updates duty cycle, frequency, and polarity at end of a PWM cycle The PWM is a configurable dual-output, dual-clockinput AMBA slave module, and connects to the APB. Advanced Audio Codec (AAC) The Advanced Audio Codec controller (AC97) includes a 5-pin serial interface to an external audio codec. The AAC link is a bi-directional, fixed rate, serial Pulse Code Modulation (PCM) digital stream, dividing each audio frame into 12 outgoing and 12 incoming data streams (slots), each with 20-bit sample resolution. The AAC controller contains logic that controls the AAC link to the audio codec and an interface to the AMBA APB. Its main features include: * Serial-to-parallel conversion for data received from the external codec * Parallel-to-serial conversion for data transmitted to the external codec * Reception/transmission of control and status information via the AMBA APB interface Advance Data Sheet 27 LH7A404 32-Bit System-on-Chip Synchronous Serial Port (SSP) The SSP is a master-only interface for synchronous serial communication with peripheral devices that have either Motorola SPI, National Semiconductor MICROWIRE, or Texas Instruments Synchronous Serial Interfaces. The SSP performs serial-to-parallel conversion on data received from a peripheral device. The transmit and receive paths are buffered with internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit and receive modes. Serial data is transmitted on SSPTXD and received on SSPRXD. The LH7A404 SSP includes a programmable bit rate clock divider and prescaler to generate the serial output clock SCLK from the input clock SSPCLK. Bit rates are supported to 2 MHz and beyond, subject to choice of frequency for SSPCLK; the maximum bit rate will usually be determined by peripheral device's capability. Timers The LH7A404 includes three programmable timers. Each of the timers can operate in two modes: free running and pre-scale. The timers are programmed using four registers; Load, Value, Control, and Clear. Two identical timers, Timer 1 (TC1) and Timer 2 (TC2), use clock sources of either 508 kHz or 2 kHz. The clock source and mode is selectable by writing to the appropriate bits in the system control register. Each timer has a 16-bit read/write data register and a control register. The timer is loaded with the value written to the data register immediately. This value is then decremented on the next active clock edge to arrive after the write. When the timer underflows, it immediately asserts its appropriate interrupt. Timer 3 (TC3) has the same basic operation, but is clocked from a single 7.3728 MHz source. Once the timer has been enabled and written to, it decrements on the next rising edge of the 7.3728 MHz clock after the data register has been updated. FREE-RUNNING MODE In free-running mode, the timer wraps around to 0xFFFF when it underflows and continues counting down. PRE-SCALE MODE In pre-scale (periodic) mode, the value written to each timer is automatically re-loaded when the timer underflows. This mode can be used to produce a programmable frequency to drive the buzzer or generate a periodic interrupt. UART/IrDA The LH7A404 contains three UARTs; UART1, UART2, and UART3. The UART performs: * Serial-to-Parallel conversion on data received from the peripheral device * Parallel-to-Serial conversion on data transmitted to the peripheral device. The transmit and receive paths can both be routed through the DMA separately or simultaneously, and are buffered with internal FIFO memories. This allows up to 16 bytes to be stored independently in both transmit and receive modes. The UART can generate: * Four individually maskable interrupts from the receive, transmit and modem status logic blocks * A single combined interrupt so that the output is asserted if any of the individual interrupts are asserted and unmasked. If a framing, parity or break error occurs during reception, the appropriate error bit is set and stored in the FIFO. If an overrun condition occurs, the overrun register bit is set immediately and the FIFO data is prevented from being overwritten. UART1 also supports IrDA 1.0 (15.2 kbit/s). The modem status input signals Clear to Send (CTS), Data Carrier Detect (DCD) and Data Set Ready (DSR) are supported on UART2 and UART3. Real Time Clock (RTC) The RTC provides a basic alarm function or long time-base counter. This is achieved by generating an interrupt signal after counting for a programmed number of cycles of a real-time clock input. Counting in one second intervals is achieved by use of a 1 Hz clock input to the RTC. 28 Advance Data Sheet 32-Bit System-on-Chip LH7A404 Keyboard and Mouse Interface (KMI) The Keyboard and Mouse Interface has the following features: * IBM PS2 or AT-compatible keyboard or mouse interface * Half-duplex bidirectional synchronous serial interface using open-drain outputs for clock and data. * Programmable 4-bit reference clock divider * Polled or interrupt-driven mode * Separately maskable transmit and receive interrupts * Single combined interrupt output * Odd parity generation and checking * Register bits for override of keyboard clock and data lines. Additional test registers and modes are implemented for functional verification and manufacturing test. Battery Monitor Interface (BMI) The BMI is a serial communication interface specified for two types of battery monitors/gas gauges. The first type employs a single wire interface. The second interface employs a two-wire multi-master bus, the Smart Battery System Specification. If both interfaces are enabled at the same time, the Single Wire Interface will have priority. SINGLE WIRE INTERFACE The Single Wire Interface performs: * Serial-to-parallel conversion on data received from the peripheral device * Parallel-to-serial conversion on data transmitted to the peripheral device * Data packet coding/decoding on data transfers (incorporating Start/Data/Stop data packets) The Single Wire interface uses a command-based protocol in which the host initiates a data transfer by sending a WriteData/Command word to the battery monitor. This word always contains the command section, which tells the Single Wire Interface device the location for the current transaction. The most significant bit of the command determines if the transaction is Read or Write. In the case of a Write transaction the word will also contain a WriteData section with the data to be written to the peripheral. SMART BATTERY INTERFACE The Smart Battery Interface performs: * Serial-to-parallel conversion on data received from the peripheral device * Parallel-to-serial conversion of data transmitted to the peripheral device. The Smart Battery Interface uses a two-wire multimaster bus (the SMBus), allowing multiple bus masters to be connected to it. A master device initiates a bus transfer and provides the clock signals. A slave device can receive data provided by the master or it can provide data to the master. Since more than one device may attempt to take control of the bus as a master, SMBus provides an arbitration mechanism by relying on the wired-AND connection of all SMBus interfaces to the SMBus. Touch Screen Controller (TSC) The Touch Screen Controller is a complete interface to a touch screen as used in portable personal devices. It combines the front-end biasing and control circuitry with analog-to-digital conversion, reference generation, and digital control and interface functions to completely replace external ICs used to implement this interface. The features are: * 10-bit A/D converter with integrated sample-andhold, fully differential, high impedance signal and reference inputs. * Input active matrix for bias and control circuits necessary for connection to external 4- and 5-wire touch sensitive panels. * Auxiliary functions such as temperature sense, pen pressure sense, battery voltage sense, in addition to normal direct voltage inputs. * A 10-channel multiplexer for routing user-selected inputs to A/D * 16 x 16 FIFO for 10-bit digital output of A/D * Pen down sensor to generate interrupts to the host * Low power circuitry and power control modes to minimize in-system power dissapation. * Conversion automation to maximize flexibility while minimizing CPU management and interrupt overhead * Supply voltage 3.0 V - 3.6 V * Configurable input pads so that when an Analog input is not being used, the pad can be used as a GPIO. Advance Data Sheet 29 LH7A404 32-Bit System-on-Chip DC-to-DC Converter The features of the DC-DC Converter interface are: * Dual drive PWM outputs with independent closed loop feedback * Software programmable configuration of one of 8 output frequencies (each being a fixed division of the input clock). * Software programmable configuration of duty cycle from 0 to 15/16, in intervals of 1/16. * Hardware-configured output polarity (for positive or negative voltage generation) during power-on reset via the polarity select inputs * Dynamically switched PWM outputs to one of a pair of preprogrammed frequency/duty cycle combinations via external pins. General Purpose I/O (GPIO) The GPIO has eight ports, each with a data register and a data direction register. It also has added registers including Keyboard Scan, PINMUX, GPIO Interrupt Enable, INTYPE1/2, GPIOFEOI and PGHCON. The data direction register determines whether a port is configured as an input or an output while the data register is used to read the value of the GPIO pins. The GPIO Interrupt Enable, INTYPE1/2, and the GPIOFEOI registers control edge-triggered Interrupts on Port F. The PINMUX register controls which signals are from Port D and Port E when they are set as outputs, while the PGHCON controls the operations of Port G and Port H. Watchdog Timer (WDT) The Watchdog Timer provides hardware protection against malfunctions. It is a programmable timer that is reset by software at regular intervals. Failure to reset the timer will cause an FIQ interrupt. Failure to service the FIQ interrupt generates a system reset. Features of the WDT: * Timing derived from the system clock * 16 programmable time-out periods: 216 through 231 clock cycles * Generates a system reset (resets LH7A404) or a FIQ interrupt whenever a time-out period is reached * Software enable, lockout, and counter-reset mechanisms add security against inadvertent writes * Protection mechanism guards against interrupt-service-failure: - The first WDT time-out triggers FIQ and asserts nWDFIQ status flag - If FIQ service routine fails to clear nWDFIQ, then the next WDT time-out triggers a system reset. 30 Advance Data Sheet 32-Bit System-on-Chip LH7A404 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings PARAMETER DC Core Supply Voltage (VDDC) DC I/O Supply Voltage (VDD) DC Analog Supply Voltage (VDDA1, VDDA2) DC Analog Supply Voltage (VDDA3) Storage Temperature MINIMUM - 0.3 V - 0.3 V - 0.3 V - 0.3 V -55C MAXIMUM 2.4 V 4.6 V 2.4 V 4.6 V 125C NOTE: These stress ratings are only for transient conditions. Operation at or beyond absolute maximum rating conditions may affect reliability and cause permanent damage to the device. Recommended Operating Conditions PARAMETER DC Core Supply Voltage (VDDC) DC I/O Supply Voltage (VDD) DC Analog Supply Voltage (VDDA1, VDDA2) DC Analog Supply Voltage (VDDA3) Clock Frequency Commercial Operating Temperature Industrial Operating Temperature MINIMUM TYPICAL MAXIMUM 1.62 V 1.62 V 1.62 V 3.0 V 10 MHz 0C -40C 25C 25C 1.8 V 3.3 V 1.8 V 3.3 V 1.98 V 3.6 V 1.98 V 3.6 V 200 MHz +70C +85C 6 2, 3, 4, 5 NOTES 1 7 NOTES: 1. Core Voltage should never exceed I/O Voltage. 2. Using 14.756 MHz Main Oscillator Crystal and 32.768 kHz RTC Oscillator Crystal. 3. Commercial Temperature Range. 4. VDDC = 1.62 V to 1.98 V. 5. VDD = 3.0 V to 3.6 V. 6. With Clock Frequency Reduction. The LH7A404 has not yet been characterized for the Industrial Temperature Range. 7. Using the LH7A404 below VDD = 3.0 V will affect the AC timing and the USB will not function. AC timing for VDD less than 3.0 V has not yet been characterized. Advance Data Sheet 31 LH7A404 32-Bit System-on-Chip DC/AC SPECIFICATIONS (COMMERCIAL) Unless otherwise noted, all data provided under commercial DC/AC specifications are based on 0C to +70C, VDDC = 1.62 V to 1.98 V, VDD = 3.3 V to 3.6 V, VDDA1 and VDDA2 = 1.62 V to 1.98 V; VDDA3 = 3.0 to 3.6 V. DC Specifications SYMBOL VIH VIL VHST PARAMETER CMOS and Schmitt Trigger Input HIGH Voltage CMOS and Schmitt Trigger Input LOW Voltage Schmitt Trigger Hysteresis CMOS Output HIGH Voltage, Output Drive 1 VOH Output Drive 2 Output Drive 3 Output Drive 4 and 5 CMOS Output LOW Voltage, Output Drive 1 Output Drive 2 VOL Output Drive 3 Output Drive 4 Output Drive 5 IIN IOZ IACTIVE IHALT ISTANDBY ISTARTUP CIN COUT Input Leakage Current Output Tri-state Leakage Current Active Current (Operating Current) Halt Current Standby Current Startup Current Input Capacitance Output Capacitance 0.35 2.6 2.6 2.6 2.6 0.0 0.0 0.0 0.0 0.0 -10 -10 3.6 3.6 3.6 3.6 0.4 0.4 0.4 0.4 0.4 10 10 180 6.0 20 50 4 4 MIN. 2.0 0.8 MAX. UNIT V V V V V V V V V V V V A A mA mA A A pF pF 2 3 4 VIL to VIH IOH = 2 mA IOH = 4 mA IOH = 8 mA IOH = 16 mA IOL = 2 mA IOL = 4 mA IOL = 8 mA IOL = 16 mA IOL = 24 mA VIN = VDD or GND VOUT = VDD or GND 1 1 CONDITIONS NOTES NOTES: 1. Output Drive 5 can sink 24 mA of current, but sources 16 mA of current. 2. Both oscillators running, LCD Active; all other peripherals stopped. 3. 32 kHz oscillator running; all other peripherals stopped. 4. Current consumption until oscillators are stabilized. AC Test Conditions PARAMETER DC I/O Supply Voltage (VDD) DC Core Supply Voltage (VDDC) Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels RATING 3.0 to 3.6 1.62 to 1.98 VSS to 3 2 VDD/2 UNIT V V V ns V 32 Advance Data Sheet 32-Bit System-on-Chip LH7A404 AC Specifications (Commercial) All signals described in Table 5 relate to transitions following a reference clock signal. The illustration in Figure 6 represents all cases of these sets of measurement parameters. The reference clock signals in this design are: * HCLK, the System Bus internal clock * PCLK, the Peripheral Bus clock * SSPCLK, the Synchronous Serial Port clock * UARTCLK, the UART Interface clock * LCDDCLK, the LCD Data clock from the LCD Controller * AC97CLK, the AC97 clock * SCLK, the Synchronous Memory clock. All signal transitions are measured from the 50% point of the clock to the 50% point of the signal. For outputs from the LH7A404, tOVXXX (e.g. tOVA) represents the amount of time for the output to become valid from the rising edge of the reference clock signal. Maximum requirements for tOVXXX are shown in Table 5. The signal tOHXXX (e.g. tOHA) represents the amount of time the output will be held valid following the rising edge of the reference clock signal. Minimum requirements for tOHXXX are listed in Table 5. For inputs, tISXXX (e.g. tISD) represents the amount of time the input signal must be valid before the rising edge of the clock signal. Minimum requirements for tISXXX are shown in Table 5. The signal tIHXXX (e.g. tIHD) represents the amount of time the output must be held valid following the rising edge of the reference clock signal. Minimum requirements are shown in Table 5. REFERENCE CLOCK tOVXXX tOHXXX OUTPUT SIGNAL (O) tISXXX tIHXXX INPUT SIGNAL (I) LH7A404-9 Figure 6. LH7A404 Signal Timing Table 5. AC Signal Characteristics SIGNAL TYPE LOAD DRIVE SYMBOL tOVA tOHA tOVD tOHD tISD tIHD 30 pF 30 pF 30 pF 30 pF 8 mA 8 mA 8 mA 8 mA tOVCS tOHCS tOVWE tOHWE tOVBLE tOHBLE tOVOE tOHOE 0 ns 0 ns 8 ns 0 ns 8 ns 0 ns 8 ns 2 ns 2 ns 0 ns 8 ns 0 ns 6 ns MIN. MAX. 8 ns DESCRIPTION Address Valid Address Hold Data Valid Data Hold Data Setup Data Hold Chip Select Valid Chip Select Hold Write Enable Valid Write Enable Hold Byte Lane Enable Valid Byte Lane Enable Hold Ouput Enable Valid Ouput Enable Hold ASYNCHRONOUS MEMORY INTERFACE SIGNALS A[27:0] Output Output D[31:0] Input nCS[7:0] nWE[3:0] nBLE[3:0] nOE Output Output Output Output 50 pF 50 pF 8 mA 8 mA Advance Data Sheet 33 LH7A404 32-Bit System-on-Chip Table 5. AC Signal Characteristics (Cont'd) SIGNAL A[15:2]/SA[13:0] A[17:16]/SBANK[1:0] D[31:0] TYPE Output Output Output Input Output Output Output Output Output Output 30 pF 30 pF 30 pF 30 pF 30 pF 30 pF 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA LOAD 50 pF 50 pF 50 pF DRIVE 8 mA 8 mA 8 mA SYMBOL tOVA tOVB tOVD tISD tIHD tOVCA tOHCA tOVRA tOHRA tOVSDW tOHSDW tOVC0 tOVDQ tOVSC tOVHSC tOVA tOVDREG tOHDREG tISD tIHD 30 pF 30 pF 30 pF 30 pF 8 mA 8 mA 8 mA 8 mA tOVCE1 tOHCE1 tOVCE2 tOHCE2 tOVOE tOHOE tOVWE tOHWE tOVCMD tOHCMD tOVDAT tOHDAT tISDAT tIHDAT tOVCMD tIHCMD tOVAC97 tOHAC97 tISAC97 tIHAC97 tISSSPFRM 50 pF 2 mA tOVSSPOUT tISSSPIN TBD TBD TBD 14 ns TBD 14 ns TBD TBD TBD TBD TBD TBD TBD TBD 2 ns 0 ns 4 ns 0 ns 0 ns 0 ns 0 ns 0 ns 0 ns 0 ns 0 ns 0 ns TBD 8 ns 8 ns 8 ns 8 ns 2 ns 4 ns 0 ns 2 ns 0 ns 2 ns 0 ns 2 ns 0 ns 2 ns 2 ns 2 ns 0 ns 8 ns 8 ns 6 ns 6 ns 6 ns 6 ns 6 ns 6 ns MIN. MAX. 8 ns 8 ns 6 ns DESCRIPTION Address Valid Address Valid/Bank Select Valid Data Valid Data Setup Data Hold CAS Valid CAS Hold RAS Valid RAS Hold Write Enable Valid Write Enable Hold Clock Enable Valid Data Mask Valid Synchronous Chip Select Valid Synchronous Chip Select Hold Address Valid nREG Valid nREG Hold Data Setup Time Data Hold Time Chip Enable 1 Valid Chip Enable 1 Hold Chip Enable 2 Valid Chip Enable 2 Hold Output Enable Valid Output Enable Hold Write Enable Valid Write Enable Hold MMC Command Valid MMC Command Hold MMC Data Valid MMC Data Hold MMC Data Setup MMC Data Hold MMC Command Setup MMC Command Hold AC97 Output Valid AC97 Output Hold AC97 Input Setup AC97 Input Hold SSPFRM Input Valid SSP Transmit Valid SSP Receive Setup SYNCHRONOUS MEMORY INTERFACE SIGNALS nCAS nRAS nSWE SCKE[1:0] DQM[3:0] nSCS[3:0] PC CARD (PCMCIA) INTERFACE SIGNALS A[25:0] nCFREG D[31:0] nCFCE1 nCFCE2 nCFOE nCFWE Output Output Input Output Output Output Output 50 pF 30 pF 8 mA 8 mA MMC INTERFACE SIGNALS MMCCMD MMCDATA MMCDATA MMCCMD Output Output Input Input 100 pF 100 pF 8 mA 8 mA AC97 INTERFACE SIGNALS AC97OUT AC97IN Output Input 30 pF 8 mA SYNCHRONOUS SERIAL PORT (SSP) SSPFRM SSPTX SSPRX Input Output Input NOTES: 1. TBD = To Be Determined, awaiting characterization. 2. For Output Drive strength specifications, refer to `DC Specifications'. 34 Advance Data Sheet 32-Bit System-on-Chip LH7A404 Asynchronous Memory Controller Waveforms Figure 7 shows the waveform and timing for an external asynchronous memory Write. Figure 8 shows the waveform and timing for an external asynchronous memory Read, with one wait state. Figure 9 shows the waveform and timing for an external asynchronous memory Read, with two wait states. HCLK A[27:0] (NOTE 1) ADDRESS tOVA D[31:0] DATA tOHA tOVD tOHD tOVD nCS(X) tOVCS nBLE[3:0], nWE NOTES: 1. A[24:0] when SCI used. 2. All signal transitions are measured from the 50% point of the clock to the 50% point of the signal. tOHCS tOVBLE, tOVWE tOHBLE, tOHWE LH7A404-10 Figure 7. External Asynchronous Memory Write DATA READ 1 WAIT STATE HCLK A[25:0] ADDRESS tOVA tOHA D[31:0] DATA tISD tIHD nCSx tOVCS nOE tOHCS tOVOE tOHOE NOTE: All signal transitions are measured from the 50% point of the clock to the 50% point of the signal. LH7A404-11 Figure 8. External Asynchronous Memory Read, One Wait State Advance Data Sheet 35 LH7A404 32-Bit System-on-Chip DATA READ 2 WAIT STATES HCLK tOHA A[25:0] ADDRESS tIHD tOVA D[31:0] DATA tISD tOHCS nCSx tOHOE tOVCS nOE tOVOE NOTE: All signal transitions are measured from the 50% point of the clock to the 50% point of the signal. LH7A404-12 Figure 9. External Asynchronous Memory Read, Two Wait States 36 Advance Data Sheet 32-Bit System-on-Chip LH7A404 Synchronous Memory Controller Waveforms Figure 10 shows the waveform and timing for a Synchronous Burst Read (page already open). Figure 11 shows the waveform and timing for synchronous memory to activate a bank and Write. tSCLK SCLK tOHXXX SDRAMcmd READ tOVB tOVXXX SA[13:0], SBANK[1:0] tOVA D[31:0] NOTES: 1. SDRAMcmd is the combination of nRAS, nCAS, nSDWE, and nSDCSx. 2. tOVXXX represents tOVRA, tOVCA, tOVSDW, or tOVSC. 3. tOHXXX represents tOHRA, tOHCA, tOHSDW, or tOHSC. 4. nDQM is static LOW. 5. SDCKE is static HIGH. BANK, COLUMN tISD tIHD DATA n + 2 DATA n DATA n + 1 DATA n + 3 LH7A404-13 Figure 10. Synchronous Burst Read tSCLK SCLK tOVC0 SDCKE tOVXXX tOHXXX SDRAMcmd ACTIVE tOVA WRITE SA[13:0], SBANK[1:0] BANK, ROW tOVA D[31:0] tOVD NOTES: 1. SDRAMcmd is the combination of nRAS, nCAS, nSDWE, and nSDCSx. 2. tOVXXX represents tOVRA, tOVCA, tOVSDW, or tOVSC. Refer to the AC timing table. 3. tOHXXX represents tOHRA, tOHCA, tOHSDW, or tOHSC. 4. nDQM is static LOW. tOHD DATA BANK, COLUMN LH7A404-14 Figure 11. Synchronous Bank Activate and Write Advance Data Sheet 37 LH7A404 32-Bit System-on-Chip SSP Waveforms The Synchronous Serial Port (SSP) supports three data frame formats: * Texas Instruments' synchronous serial * Motorola SPI * National Semiconductor MICROWIRE Each frame format is between 4 and 16 bits in length, depending upon the programmed data size. Each data frame is transmitted beginning with the Most Significant Bit (MSB) i.e. `big endian'. For all three formats, the SSP serial clock is held LOW (inactive) while the SSP is idle. The SSP serial clock transitions only during active transmission of data. The SSPFRM signal marks the beginning and end of a frame. The SSPEN signal controls an off-chip line driver's output enable pin. Figure 12 and Figure 13 show Texas Instruments synchronous serial frame format, Figure 14 through Figure 21 show the Motorola SPI format, and Figure 22 and Figure 23 show National Conductor's MICROWIRE data frame format. For Texas Instruments' synchronous serial frame format, the SSPFRM pin is pulsed prior to each frame's transmission for one serial clock period beginning at its rising edge. For this frame format, both the SSP and the external slave device drive their output data on the rising edge of the clock and latch data from the other device on the falling edge. See Figure 12 and Figure 13. SSPCLK SSPFRM SSPTXD/ SSPRXD MSB 4 to 16 BITS LSB LH7A404-24 Figure 12. Texas Instruments Synchronous Serial Frame Format (Single Transfer) SSPCLK SSPFRM SSPTXD/ SSPRXD MSB 4 to 16 BITS LH7A404-25 LSB Figure 13. Texas Instruments Synchronous Serial Frame Format (Continuous Transfer) 38 Advance Data Sheet 32-Bit System-on-Chip LH7A404 For Motorola SPI format, the serial frame pin (SSPFRM) is active LOW. The SPO and SPH bits in SSP Control Register 0 determine SSPCLK and SSPFRM operation in single and continuous modes. See Figures 14 through 21. SSPCLK nSSPFRM SSPRXD MSB 4 to 16 BITS LSB Q SSPTXD NOTE: Q is undefined. MSB LSB LH7A404-26 Figure 14. Motorola SPI Frame Format (Single Transfer) with SPO = 0 and SPH = 0 SSPCLK nSSPFRM SSPTXD/ SSSRXD LSB MSB 4 to 16 BITS LSB MSB LH7A404-27 Figure 15. Motorola SPI Frame Format (Continuous Transfer) with SPO = 0 and SPH = 0 SSPCLK nSSPFRM SSPRXD Q MSB LSB Q 4 to 16 BITS SSPTXD NOTE: Q is undefined. MSB LSB LH7A404-28 Figure 16. Motorola SPI Frame Format (Single Transfer) with SPO = 0 and SPH = 1 Advance Data Sheet 39 LH7A404 32-Bit System-on-Chip SSPCLK nSSPFRM SSPTXD/ SSSRXD LSB MSB 4 to 16 BITS LSB MSB LH7A404-29 Figure 17. Motorola SPI Frame Format (Continuous Transfer) with SPO = 0 and SPH = 1 SSPCLK nSSPFRM SSPTXD/ SSSRXD LSB MSB 4 to 16 BITS LSB MSB LH7A404-30 Figure 18. Motorola SPI Frame Format (Continuous Transfer) with SPO = 1 and SPH = 1 SSPCLK nSSPFRM SSPRXD MSB LSB Q 4 to 16 BITS SSPTXD MSB LSB NOTE: Q is undefined. LH7A404-31 Figure 19. Motorola SPI Frame Format (Single Transfer) with SPO = 1 and SPH = 0 40 Advance Data Sheet 32-Bit System-on-Chip LH7A404 SSPCLK nSSPFRM SSPTXD/ SSPRXD LSB MSB LSB MSB 4 to 16 BITS LH7A404-32 Figure 20. Motorola SPI Frame Format (Continuous Transfer) with SPO = 1 and SPH = 0 SSPCLK nSSPFRM SSPRXD Q MSB LSB Q 4 to 16 BITS SSPTXD NOTE: Q is undefined. MSB LSB LH7A404-33 Figure 21. Motorola SPI Frame Format (Single Transfer) with SPO = 1 and SPH = 1 Advance Data Sheet 41 LH7A404 32-Bit System-on-Chip For National Semiconductor MICROWIRE format, the serial frame pin (SSPFRM) is active LOW. Both the SSP and external slave device drive their output data on the falling edge of the clock, and latch data from the other device on the rising edge of the clock. Unlike the full-duplex transmission of the other two frame formats, the National Semiconductor MICROWIRE format utilizes a master-slave messaging technique that operates in half-duplex. When a frame begins in this mode, an 8-bit control message is transmitted to the off-chip slave. During this transmission no incoming data is received by the SSP. After the message has been sent, the external slave device decodes the message. After waiting one serial clock period after the last bit of the 8bit control message was received it responds by returning the requested data. The returned data can be 4 to 16 bits in length, making the total frame length between 13 to 25 bits. See Figure 22 and Figure 23. SSPCLK nSSPFRM SSPTXD MSB LSB 8-BIT CONTROL SSPRXD 0 MSB LSB 4 to 16 BITS OUTPUT DATA LH7A404-34 Figure 22. MICROWIRE Frame Format (Single Transfer) SSPCLK nSSPFRM SSPTXD LSB MSB LSB 8-BIT CONTROL SSPRXD 0 MSB LSB MSB 4 to 16 BITS OUTPUT DATA LH7A404-35 Figure 23. MICROWIRE Frame Format (Continuous Transfers) 42 Advance Data Sheet 32-Bit System-on-Chip LH7A404 PC Card (PCMCIA) Waveforms Figure 24 shows the waveforms and timing for a PCMCIA attribute memory Read transfer, Figure 25 shows the waveforms and timing for a PCMCIA attribute memory Write transfer, Figure 26 shows the waveforms and timing for a PCMCIA common memory Read transfer, and Figure 27 shows the waveforms and timing for a PCMCIA common memory Write transfer. HCLK tOVA A[25:0] tOVDREG nCFREG tOVCE1 nCFCE1 tOHCE1 tOHDREG tOHA nCFCE2 tOVOE tOHOE nCFOE nCFWE tISD tIHD D[31:0] D[7:0] (EVEN BYTE) LH7A404-15 Figure 24. PCMCIA Attribute Memory Read Transfer Advance Data Sheet 43 LH7A404 32-Bit System-on-Chip HCLK tOVA A[25:0] tOHA nCFREG tOVCE1 tOHCE1 nCFCE1 nCFCE2 nCFOE tOVWE tOHWE nCFWE tISD tIHD D[31:0] D[7:0] (EVEN BYTE) LH7A404-16 Figure 25. PCMCIA Attribute Memory Write Transfer 44 Advance Data Sheet 32-Bit System-on-Chip LH7A404 HCLK tOVA A[25:0] tOHA nCFREG tOVCE1 nCFCE1 tOVCE2 nCFCE2 tOVOE tOHOE tOHCE2 tOHCE1 nCFOE nCFWE tISD tIHD D[31:0] D[15:0] (WORD) LH7A404-17 Figure 26. PCMCIA Common Memory Read Transfer Advance Data Sheet 45 LH7A404 32-Bit System-on-Chip HCLK tOVA A[25:0] tOHA nCFREG tOVCE1 nCFCE1 tOVCE2 nCFCE2 tOHCE2 tOHCE1 nCFOE tOVOE tOHOE nCFWE tISD D[31:0] D[15:0] (WORD) LH7A404-18 tIHD Figure 27. PCMCIA Common Memory Write Transfer 46 Advance Data Sheet 32-Bit System-on-Chip LH7A404 MMC Interface Waveforms Figure 28 shows the waveforms and timing for an MMC command or data Write. Figure 29 shows the waveforms and timing for an MMC command or data Read. AC97 Interface Waveforms Figure 30 shows the waveforms and timing for the AC97 interface Data Setup and Hold. MMCCLK MMCCMD tOVCMD MMCDAT tOVDAT tOHDAT LH7A404-19 tOHCMD Figure 28. MMC Command/Data Write MMCCLK MMCCMD tIOVCMD tIHCMD MMCDAT tISDAT tIHDAT LH7A404-20 Figure 29. MMC Command/Data Read AC97SYNC tOVAC97 AC97OUT tISAC97 tIHAC97 AC97IN LH7A404-21 tOHAC97 Figure 30. AC97 Data Setup and Hold Advance Data Sheet 47 LH7A404 32-Bit System-on-Chip Reset, Clock, and Power Controller (RCPC) Waveforms Figure 31 shows the behavior of the LH7A404 when coming out of Reset or Power-On. Figure 32 shows external reset timing, and Table 6 gives the timing parameters. Table 6. Reset AC Timing PARAMETER tOSC (32 kHz) tOSC (14 MHz) tRSTIW tRSTOV tRSTOH DESCRIPTION Oscillator stabilization time after Power Up (VDDC = VDDCMIN) Oscillator stabilization time after Power Up (VDDC = VDDCMIN) nRESETIN Pulse Width (once sampled LOW) nRESETIN LOW to nRESETOUT valid (once nRESETIN sampled LOW) nRESETOUT hold relative to nRESETIN HIGH 2 3.5 1 MIN. TYP. MAX. 550 2.5 UNIT ms ms HCLK HCLK HCLK NOTE: *VDDC = VDDCmin VDDCmin VDDC XTAL tOSC nRESETI LH7A404-22 Figure 31. PLL Start-up tRSTIW nRESETI LH7A404-23 Figure 32. External Reset 48 Advance Data Sheet 32-Bit System-on-Chip LH7A404 DC/AC SPECIFICATIONS (INDUSTRIAL) To be determined. Advance Data Sheet 49 LH7A404 32-Bit System-on-Chip PACKAGE SPECIFICATIONS 324-BALL PBGA TOP VIEW 23.00 19.50 -0.05 A1 BALL PAD CORNER 7.35 B 5.17 7.35 16.15 MAX. 19.50 -0.05 +0.70 +0.70 0.20 (4X) A AVAILABLE MARKING AREA 5.17 45 CHAMFER 4 PLACES 16.15 MAX. A1 BALL PAD CORNER Z 23.00 A1 BALL PAD INDICATOR, 1.0 DIA. 0.35 Z 0.25 Z 0.15 Z BOTTOM VIEW (324 solder balls) 22 20 18 16 14 12 10 8 6 42 20 19 17 15 13 11 9 7531 SIDE VIEW A B C D E F G H J K L M N P R T U V W Y AA AB 30 TYP. 0.63 -0.13 +0.07 0.30 M C A B 0.10 M C 1.00 REF. SEATING PLANE 1.00 REF. 1.00 0.50 R, 3 PLACES 1.17 0.05 2.23 0.21 0.50 0.10 0.56 0.06 NOTE: Dimensions in mm. 324PBGA Figure 33. 324-Ball PBGA Package Specification 50 Advance Data Sheet LH7A404 32-Bit System-on-Chip SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited Warranty for SHARP's product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible, for any incidental or consequential economic or property damage. NORTH AMERICA EUROPE JAPAN SHARP Microelectronics of the Americas 5700 NW Pacific Rim Blvd. Camas, WA 98607, U.S.A. Phone: (1) 360-834-2500 Fax: (1) 360-834-8903 www.sharpsma.com SHARP Microelectronics Europe Division of Sharp Electronics (Europe) GmbH Sonninstrasse 3 20097 Hamburg, Germany Phone: (49) 40-2376-2286 Fax: (49) 40-2376-2232 www.sharpsme.com SHARP Corporation Electronic Components & Devices 22-22 Nagaike-cho, Abeno-Ku Osaka 545-8522, Japan Phone: (81) 6-6621-1221 Fax: (81) 6117-725300/6117-725301 www.sharp-world.com TAIWAN SINGAPORE KOREA SHARP Electronic Components (Taiwan) Corporation 8F-A, No. 16, Sec. 4, Nanking E. Rd. Taipei, Taiwan, Republic of China Phone: (886) 2-2577-7341 Fax: (886) 2-2577-7326/2-2577-7328 SHARP Electronics (Singapore) PTE., Ltd. 438A, Alexandra Road, #05-01/02 Alexandra Technopark, Singapore 119967 Phone: (65) 271-3566 Fax: (65) 271-3855 SHARP Electronic Components (Korea) Corporation RM 501 Geosung B/D, 541 Dohwa-dong, Mapo-ku Seoul 121-701, Korea Phone: (82) 2-711-5813 ~ 8 Fax: (82) 2-711-5819 CHINA HONG KONG SHARP Microelectronics of China (Shanghai) Co., Ltd. 28 Xin Jin Qiao Road King Tower 16F Pudong Shanghai, 201206 P.R. China Phone: (86) 21-5854-7710/21-5834-6056 Fax: (86) 21-5854-4340/21-5834-6057 Head Office: No. 360, Bashen Road, Xin Development Bldg. 22 Waigaoqiao Free Trade Zone Shanghai 200131 P.R. China Email: smc@china.global.sharp.co.jp SHARP-ROXY (Hong Kong) Ltd. 3rd Business Division, 17/F, Admiralty Centre, Tower 1 18 Harcourt Road, Hong Kong Phone: (852) 28229311 Fax: (852) 28660779 www.sharp.com.hk Shenzhen Representative Office: Room 13B1, Tower C, Electronics Science & Technology Building Shen Nan Zhong Road Shenzhen, P.R. China Phone: (86) 755-3273731 Fax: (86) 755-3273735 (c)2002 by SHARP Corporation Reference Code SMA02004 |
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